Diode clamped solid-state circuit breaker without dynamic voltage balancing issues

ABSTRACT

Various examples are provided related to diode clamped solid-state circuit breakers (SSCBs). Their configuration allows operation of the SSCB without dynamic voltage balancing issues. In one example, a diode clamped SSCB includes source-side switches and line-side switches connected between a DC source connection and a line-side connection. Clamping capacitors are connected at a common connection point between the source-side and line side switches and source-side and line-side clamping diodes are connected between the source-side switches and line-side switches and the clamping capacitors. Sequential switching of the source-side switches or line-side switches can avoid dynamic voltage balancing issues.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority to, and the benefit of, co-pending U.S.provisional application entitled “Novel Diode-Clamped Solid-StateCircuit Breaker Without Dynamic Voltage Balancing Issues” having Ser.No. 62/896,022, filed on Sep. 5, 2020, which is hereby incorporated byreference in its entirety.

BACKGROUND

Low-voltage solid-state circuit breakers (SSCBs) rated up to 1 kV havegradually matured and came to marketing, fueled by the introduction ofwide band gapped (WBG) semiconductor devices. However, to break into ahigher voltage range, stringing available to lower voltage devices inseries is required. This causes issues with the balancing of the blockedvoltage across the cascaded devices during on/off transient operation.The series-connected devices may fail to turn off simultaneously due tominute differences in device characteristics and responsiveness of thegate drivers, which can result in one of the devices bearing the bruntof the circuit voltage leading to an overvoltage device failure. Currentpractice suggests several auxiliary circuit designs to resolve thisissue, but those typically increase complexity of SSCBs and decreasetheir reliability.

SUMMARY

Aspects of the present disclosure are related to diode clampedsolid-state circuit breakers (SSCBs). A novel diode clamped SSCB isdisclosed which can address voltage balancing issues encountered instate-of-the-art cascaded device topologies for SSCBs. Rather than turnoff the switching devices simultaneously as what happens in traditionalSSCB cascaded topologies, the disclosed topology turns off thesemiconductor devices sequentially while clamping the turn off voltageacross each switching device, providing a balanced turn off voltagedistribution.

In one aspect, among others, a diode clamped solid-state circuit breaker(SSCB) comprises a series of N source-side switches connected in seriesbetween a first DC source connection and a common connection point, aseries of N line-side switches connected in series between a line-sideconnection and the common connection point, and a series of N clampingcapacitors connected in series between a second DC source connection andthe common connection point. The series of N source-side switches cancomprise a first source-side switch connected to the first DC sourceconnection and a second source-side switch connected adjacent to thefirst source-side switch; the series of N line-side switches cancomprise a first line-side switch connected to the line-side connectionand a second line-side switch connected adjacent to the first line-sideswitch; and the series of N clamping capacitors can comprise a firstclamping capacitor connected to the second DC source connection and asecond clamping capacitor connected adjacent to the first clampingcapacitor. A source-side surge protector can be connected across thefirst source-side switch and a line-side surge protector can beconnected across the first line-side switch. A source-side clampingdiode can be connected at a first end between the first and secondsource-side switches and at a second end between the first and secondclamping capacitors and a line-side clamping diode can be connected at afirst end between the first and second line-side switches and at asecond end between the first and second clamping capacitors. N can begreater than two.

In one or more aspects, the SSCB can comprise control circuitryconfigured to control switching of the series of N source-side switchesin response to a detected source-side fault and the series of Nline-side switches in response to a detected line-side fault. Thecontrol circuitry can comprise gate drivers associated with the seriesof N source-side switches and the series of N line-side switches. Thecontrol circuitry can sequentially turn off the series of N source-sideswitches from an N-th source-side switch to the first source-side switchin response to the detected source-side fault. The control circuitry canturn off the second source-side switch before turning off the firstsource-side switch. The control circuitry can sequentially turn off theseries of N line-side switches from an N-th line-side switch to thefirst line-side switch in response to the detected line-side fault. Thecontrol circuitry can turn off the second line-side switch beforeturning off the first line-side switch.

In various aspects, the SSCB can comprise a second source-side clampingdiode connected at a first end between the second source-side switch anda third source-side switch connected adjacent to the second source-sideswitch, and at a second end between the second clamping capacitor and athird clamping capacitor of the series of N clamping capacitors, thethird clamping capacitor connected adjacent to the second clampingcapacitor; and a second line-side clamping diode connected at a firstend between the second line-side switch and a third line-side switchconnected adjacent to the second line-side switch, and at a second endbetween the second clamping capacitor and the third clamping capacitor.The first and second clamping capacitors can have equal capacitance ordifferent capacitances. The capacitance of the first clamping capacitorcan be greater than the capacitance of the second clamping capacitor.

In some aspects, the SSCB can comprise control circuitry configured tosequentially turn off the series of N source-side switches in responseto the detected source-side fault, wherein the control circuitry turnsoff the third source-side switch before turning off the secondsource-side switch, and turns off the second source-side switch beforeturning off the first source-side switch. The SSCB can comprise controlcircuitry configured to sequentially turn off the series of N line-sideswitches in response to the detected line-side fault, wherein thecontrol circuitry turns off the third line-side switch before turningoff the second line-side switch, and turns off the second line-sideswitch before turning off the first line-side switch.

In another aspect, a method comprises supplying DC voltage through adiode clamped solid-state circuit breaker (SSCB) by turning on a seriesof N source-side switches and a series of N line-side switches of theSSCB, the series of N source-side switches connected in series between afirst DC source connection and the common connection point and a seriesof N line-side switches connected in series between a line-sideconnection and the common connection point; detecting a source-sidefault or a line-side fault; and sequentially turning off the series of Nsource-side switches from an N-th source-side switch to the firstsource-side switch in response to the detected source-side fault orsequentially turning off the series of N line-side switches from an N-thline-side switch to the first line-side switch in response to thedetected line-side fault.

The series of N source-side switches can comprise a first source-sideswitch connected to the first DC source connection and a secondsource-side switch connected adjacent to the first source-side switch,and the series of N line-side switches comprising a first line-sideswitch connected to the line-side connection and a second line-sideswitch connected adjacent to the first line-side switch. The SSCB canfurther comprise a series of N clamping capacitors connected in seriesbetween a second DC source connection and the common connection point,N−1 source-side clamping diodes each connected between different pairsof adjacent source-side switches in the series of N source-side switchesand different pairs of adjacent clamping capacitors in the series of Nclamping capacitors, and N−1 line-side clamping diodes each connectedbetween different pairs of adjacent line-side switches in the series ofN line-side switches and the different pairs of adjacent clampingcapacitors.

The second source-side switch can be turned off before the firstsource-side switch is turned off to direct current flow through a firstclamping capacitor of the series of N clamping capacitors and one of theN−1 source-side clamping diodes and the first source-side switch isturned off to the direct current flow through a surge protectorconnected across the first source-side switch. The second line-sideswitch can be turned off before the first line-side switch is turned offto direct current flow through the first clamping capacitor and one ofthe N−1 line side clamping diodes and the first line-side switch isturned off to the direct current flow through a surge protectorconnected across the first line-side switch.

In one or more aspects, N can equal two and the series of N clampingcapacitors can comprise the first clamping capacitor and a secondclamping capacitor, wherein the first and second clamping capacitorshave equal capacitance or a capacitance of the first clamping capacitorcan be greater than a capacitance of the second clamping capacitor.Sequentially turning off the series of N source-side switches cancomprise turning off a third source-side switch before the secondsource-side switch is turned off to direct current flow through thefirst clamping capacitor and a second clamping capacitor and another oneof the N−1 source-side clamping diodes. Sequentially turning off theseries of N line-side switches can comprise turning off a thirdline-side switch before the second line-side switch is turned off todirect current flow through the first clamping capacitor and a secondclamping capacitor and another one of the N−1 line-side clamping diodes.Each clamping capacitor of the series of N clamping capacitors can havea different capacitance.

Other systems, methods, features, and advantages of the presentdisclosure will be or become apparent to one with skills in the art uponexamination of the following drawings and detailed description. It isintended that all such additional systems, methods, features, andadvantages be included within this description, be within the scope ofthe present disclosure, and be protected by the accompanying claims. Inaddition, all optional and preferred features and modifications of thedescribed embodiments are usable in all aspects of the disclosure taughtherein. Furthermore, the individual features of the dependent claims, aswell as all optional and preferred features and modifications of thedescribed embodiments are combinable and interchangeable with oneanother.

BRIEF DESCRIPTION OF THE DRAWINGS

Many aspects of the present disclosure can be better understood withreference to the following drawings. The components in the drawings arenot necessarily to scale, emphasis instead being placed upon clearlyillustrating the principles of the present disclosure. Moreover, in thedrawings, like reference numerals designate corresponding partsthroughout the several views.

FIG. 1 is a schematic diagram illustrating an example of a conventionalsolid-state circuit breaker (SSCB) topology with series connectedswitches, in accordance with various embodiments of the presentdisclosure.

FIG. 2 illustrates an example of a dynamic voltage unbalancing issuecaused by the asynchronous gate delay in the conventional SSCB topologyof FIG. 1, in accordance with various embodiments of the presentdisclosure.

FIG. 3 is a schematic diagram illustrating an example of a diode clampedSSCB topology, in accordance with various embodiments of the presentdisclosure.

FIGS. 4A, 4B and 4C illustrate subinterval modes of operation of thediode clamped SSCB topology of FIG. 3 during a line-side fault, inaccordance with various embodiments of the present disclosure.

FIGS. 5, 6 and 7 illustrate examples of simulated line current andswitch voltages in the diode clamped SSCB topology of FIG. 3 withsymmetrical and asymmetrical configurations, in accordance with variousembodiments of the present disclosure.

FIG. 8 is an image showing a fabricated diode clamped SSCB topology, inaccordance with various embodiments of the present disclosure.

FIGS. 9, 10 and 11 illustrate examples of experimental line current andswitch voltages in the diode clamped SSCB topology of FIG. 8 withsymmetrical and asymmetrical configurations, in accordance with variousembodiments of the present disclosure.

FIG. 12 is a schematic diagram illustrating an extension of the diodeclamped SSCB topology to three levels, in accordance with variousembodiments of the present disclosure.

DETAILED DESCRIPTION

Disclosed herein are various examples related to diode clampedsolid-state circuit breakers and their operation without dynamic voltagebalancing issues. Reference will now be made in detail to thedescription of the embodiments as illustrated in the drawings, whereinlike reference numbers indicate like parts throughout the several views.

A solid-state circuit breaker (SSCB), a semiconductor device-based faultcurrent interruption technology, outperforms traditionalelectro-mechanical circuit breakers in many aspects. In comparison witha conventional mechanical circuit breaker, the SSCB can desist fromfault current in a much faster speed without an electric arc. Withproper fault detection devices, the fault current in the SSCB can beinterrupted before the current increases too much, which makes itespecially superior to mechanical circuit breakers in the protection ofDC systems, such as shipboard and DC micro grid applications.

In recent years, low-voltage SSCBs have gradually become technicallymature and started to come into market. FIG. 1 shows a simplifiedschematic diagram illustrating an example of a conventional mediumvoltage SSCB with series connected switches. However, with the incrementof operating voltage demand, the series-connected switches can result indynamic voltage-imbalance issues among the switches. Theseries-connected devices may fail to turn off simultaneously due todevice parasitic capacitance mismatch and turn-off delay timesoriginating from the gate drivers. As a result, dynamic overvoltage canarise across a single switch. FIG. 2 illustrates an example of a dynamicvoltage unbalancing issue in a conventional SSCB with series-connectedswitches. Several auxiliary circuits dealing with the voltage dynamicunbalancing issue have been proposed, but these auxiliary circuitsincrease the complexity of SSCBs and decrease their reliability.

To address the above issues, a new type of SSCB topology named a diodeclamped SSCB is presented in this disclosure. FIG. 3 illustrates anexample of a diode clamped SSCB, which includes a series of source-sideswitches (e.g., S₁, S₂) 303 and a series of line-side switches (e.g.,S₃, S₄) 306 connected to a transmission line (L). A series of clampingcapacitors (e.g., C_(DC1), C_(DC2)) 309 is connected from a ground orneutral line to a connection point between the series of source-sideswitches 303 and the series of line-side switches 306. Clamping diodes(e.g., D₁, D₂) 312 are connected between pairs of adjacent source-sideswitches 303 or line-side switches 306 and between a corresponding pairof clamping capacitors 309 as illustrated in FIG. 3.

In the diode clamped SSCB, switches are turned off successively ratherthan simultaneously to interrupt the line current. During the breakingprocess, the voltages across the switches are clamped by the clampingcapacitors and MOVs in the breaker and therefore can be maintained lowerthan the blocking voltage of the switching devices. In the diode clampedSSCB, the design requirements for clamping voltage and energy absorptionof the MOVs are lower than in the conventional SSCB, and henceseries-connected MOVs with a large total clamp voltage can be saved. Inaddition, an asymmetric configuration of the diode clamped SSCB may alsobe used to limit the increment of fault current, shorten currentbreaking period and reduce the size of MOVs in the breaker. Theoperation principles, design consideration and experimental results ofthis novel topology under symmetric and asymmetric configurations arepresented next.

Operating Principle

In the proposed diode clamped SSCB topology, the voltage across theswitches is clamped by the capacitors and diodes. Therefore, theswitches can be turned off successively rather than simultaneouslyduring the faults. This topology allows the use of cheaper and lessbulky MOVs rated at half the SSCB voltage rating. The modes of operationin the event of a line-side fault and simulation voltage and currentwaveforms will be discussed with respect to FIGS. 4A-4C, 5 and 6.Whenever a line-side fault is detected, a first switch will turn off andthe fault current commutes through a clamping diode D1. During thismode, the voltage across the fault is a portion of (e.g., half) the DCbus voltage reducing energization of line inductance and hence growth offault current. Additional switches can be turned off to further reducethe voltage across the fault. After a dead-time period, another switchis turned off switching the fault current to a surge protector (e.g.,MOV) which absorbs the line energy reducing the fault current to zero.This switching sequence ensures that switching devices will share the DCbus voltage at the end of the turn off event, and each will notencounter a voltage higher than their individual blocking capacity intransient. Therefore, intricate auxiliary circuits for transient voltagebalancing are not needed and regular gate drivers can be used.

Diode Clamped SSCB with Symmetric Configuration.

In the diode clamped SSCB with symmetric configuration, the clampingcapacitors, C_(DC1) and C_(DC2), have the same capacitance(C_(DC1)=C_(DC2)) and share the DC bus voltage (V_(DC)) equally. Afterthe switches are turned off, the voltages across the switches will beclamped to the voltage of the clamping capacitors, equaling half of theDC bus voltage. In principle, the operating voltage of the breaker willbe twice the rated voltage of the employed semiconductor devices. Thisis one of the advantages of the diode clamped SSCB with symmetricconfiguration.

As shown in FIG. 3, the circuit of the diode clamped SSCB ishorizontally symmetrical and thus the breaker can be used to interruptbi-directional fault currents. In other words, the breaker can clear thefaults occurring either on the DC bus or transmission line. However, thecapability of the breaker to clear the DC bus fault is limited by theresonance between the line inductor and clamping capacitors. Hence, thebidirectional protection can only be achieved by the breaker in theapplications with limited line inductances, such as shipboardapplications. Since the operating process of the breaker in the twofault scenarios is similar, only the operation of the breaker forline-side faults is discussed here. The operation subintervals of thediode clamped SSCB of FIG. 3 while dealing with a line-side fault areshown in FIGS. 4A-4C. Simulation waveforms depicting the line current aswell as the voltages across the line-side switches 306 are shown in FIG.5 with the diode clamped SSCB in the symmetric configuration. Thesimulation waveforms of FIG. 5 are based upon a diode clamped SSCB in asymmetric configuration with C_(DC1)=C_(DC2=0.5) mF, V_(DC)=1000V, andI_(load)=40 A.

During normal operation, all the switches 303 and 306 are turned on toenable the conduction path through the diode clamped SSCB as shown inFIG. 4A. Whenever the relay detects a line-side fault current, controlcircuitry will trip a first line-side switch S₃ to open and transfer thefault current to the conduction loop through the clamping capacitors 309as shown in FIG. 4B. During this subinterval, the voltage across thefault is decreased to half of the DC bus voltage, so the increment ofthe fault current slows down as shown during the interval from t₁ to t₂in FIG. 5.

After a short period of delay time, a second switch S₄ is turned off andthe fault current commutes into MOV₂ 315 where the energy stored in thetransmission line is absorbed as shown in FIG. 4C. After that, the faultcurrent decreases gradually to zero as shown during the interval from t₂to t₃ in FIG. 5. It can be seen from the waveforms of the voltagesacross switches S₃ and S₄, that the two switches are not turned off atthe same time and there is no overvoltage imposed on either of theswitches during the breaking process. This demonstrates that theproposed diode clamped SSCB does not suffer from dynamic voltageunbalancing issues.

Diode Clamped SSCB with Asymmetric Configuration. An asymmetricconfiguration with the capacitance of one capacitor less than the othercapacitor (e.g., C_(DC1)<C_(DC2)) can be applied to diode clamped SSCBto restrain the increment of fault current during the delay time andshorten the breaking time of the breaker. The charge Q held by theseries connected capacitors, C_(DC1) and C_(DC2), can be given by:

Q=C _(DC1) V _(C1) =C _(DC2) V _(C2)  (1)

According to Equation (1), the voltage shared by each of the capacitorsis inversely proportional to their capacitances. Hence, the voltage ofC_(DC2), V_(C2), is lower than V_(C1), in the asymmetric configuration.The operating process of the diode clamped SSCB in an asymmetricconfiguration is the same as that in the symmetric configuration asshown in FIGS. 4A-4C.

FIG. 6 shows the simulation waveforms of the line current and voltageacross each of the line-side switches with the diode clamped SSCB in theasymmetric configuration. In this case, C_(DC2)=0.5 mF=9×C_(DC1),V_(DC)=1000V, and I_(load)=40 A. During the interruption process, assoon as the switch S₃ is open, the voltage across the faultedtransmission line drops from V_(DC) to V_(C2) which is relatively smallin the asymmetric configuration. In this way, the increment of faultcurrent can be limited as shown in the waveform of line current duringthe interval from t₁ to t₂ in FIG. 6.

The asymmetric configuration can also shorten the breaking time of theconverter. The breaking time here refers to the time spent by thebreaker from receiving the trip signal to decreasing the line current toleakage current level. In FIG. 6, the breaking time is the time intervalbetween t₁ and t₃. In order to attain accurate analysis results for theperformance of the breaker, the response time of relay is neglected.Thus, the breaking time can be mainly separated into two time periods,namely the delay time between the operation of S₃ and S₄ calledt_(delay), and the time for the MOV to absorb the energy called t_(mov).The value of t_(delay) depends on the performance of the switchingdevices as well as the gate drivers and it is usually the constant value(t₂−t₁) depicted in FIGS. 5 and 6. The value of the breaking time(t_(brk)) can be expressed as:

$\begin{matrix}{{t_{brk} = {{t_{delay} + t_{mov}} = {t_{delay} + \frac{{LI}_{0} + {V_{c\; 2}t_{delay}}}{V_{clamp} - V_{c\; 2}}}}},} & (2)\end{matrix}$

where V_(clamp) represents the clamping voltage of MOVs and L representsthe equivalent inductance of the transmission line. From Equation (2),the breaking time of the breaker is proportional to the value of V_(C2).Therefore, in the diode clamped SSCB, the breaking time can be reducedby applying an asymmetric configuration to reduce the voltage valueacross capacitor C_(DC2). However, in contrast to this benefit, thediode clamped SSCB partially loses its capability to enhance itsoperating voltage resulting from higher peak inverse voltage (PIV)imposed on switch S₃ as shown in FIG. 6. The main motivation of using anasymmetric configuration in the diode clamped SSCB is to shorten itsbreaking time. The breaking speed of the diode clamped SSCB inasymmetric configuration can be faster than the conventional breaker forthe same applied system and fault situation as shown in FIG. 7, which isa comparison of the simulation waveforms of the line currents in theconventional and diode clamped SSCBs.

Design Considerations

In order to warrant the normal operation of the diode clamped SSCB,several technical considerations were considered during the design ofthe breaker in either symmetric or asymmetric configuration. First, thecapacitances of the clamping capacitors, C_(DC1) and C_(DC2), should tobe selected carefully to avert overvoltage being imposed on switchingdevices after the current interruption. Second, the energy to beabsorbed during the breaking process should be quantified to make surethe energy volume of the selected MOV is large enough for the situation.Finally, special consideration should be taken in the selection of thesemiconductor devices in the breaker design to make the selected devicessatisfy the operating voltage, operating current and conductionefficiency of the applied system.

Capacitor Selection.

In FIGS. 4B and 4C, after switch S₃ opens, line current is transferredto the conduction loops discharging capacitor C_(DC2) and chargingC_(DC1). At the same time, the voltage across C_(DC2), V_(C2), decreasesgradually and the voltage V_(C1) increases until the line current isextinguished by the breaker. As the voltage across S₃ is clamped bycapacitor after the breaking process, the value of V_(C1) should belimited below the rated voltage of S₃ to avert impairing the switchingdevice. In other words, the increment of V_(C1) during the breakingprocess should be suppressed, which can be achieved by the properselection of the capacitors.

If the breaker detects the fault and starts to operate at the timeinstant when t=0, the increment of V_(C1) in the breaking process can beexpressed as:

$\begin{matrix}{{{\Delta \; V_{c\; 1}} = {{{- \Delta}\; V_{c\; 2}} = {{\frac{1}{c}{\int_{0}^{t_{brk}}{i_{c\; 2}{dt}}}} = {{\frac{1}{c}{\int_{0}^{t_{brk}}{i_{L}{dt}}}} = {{\frac{1}{c_{D\; C\; 2}}{\int_{0}^{t_{brk}}{\left( {I_{0} + {\frac{V_{C\; 2}(t)}{L}t}} \right){dt}}}} + {\frac{1}{c_{D\; C\; 2}}{\int_{delay}^{t_{brk}}{\left\lbrack {I_{0} + {\frac{V_{C\; 2}(t)}{L}t_{delay}} + {\frac{{V_{C\; 2}(t)} - V_{clamp}}{L}\left( {t - t_{delay}} \right)}} \right\rbrack {dt}}}}}}}}},} & (3)\end{matrix}$

where the effect of the switching transience is neglected, I_(L)represents line current and I₀ represents threshold current of thebreaker. From Equation (3), the range of capacitances of C_(DC2) thatmake the voltage across S₃ lower than its rated voltage can bedetermined and expressed as:

$\begin{matrix}{{C_{D\; C\; 2} > {\frac{\int_{0}^{t_{brk}}{\left( {I_{0} + {\frac{V_{C\; 2}(t)}{L}t}} \right){dt}}}{{{Vs}\; 3^{*}} - {V_{\; {c\; 1}}(0)}} + \frac{\int_{t_{delay}}^{t_{brk}}{\left\lbrack {I_{0} + {\frac{V_{C\; 2}(t)}{L}t_{delay}} + {\frac{{V_{C\; 2}(t)} - V_{clamp}}{L}\left( {t - t_{delay}} \right)}} \right\rbrack {dt}}}{{{Vs}\; 3^{*}} - {V_{c\; 1}(0)}}}},} & (4)\end{matrix}$

where rated voltage of Switch S₃ is denoted as Vs3*.

Since the value of V_(C2) monotonically decreases during theinterruption period and the value of the right side of Equation (4) isproportional to V_(C2), V_(C2)(t) can be replaced by V_(C2)(0) tosimplify the algebraic analysis without impairing the plausibility ofthe expression. After t_(brk) in Equation (2) is introduced intoEquation (4), the range of C_(DC2) can be determined from severaleasy-access parameters of the breaker and its applied system as shownin:

$\begin{matrix}{{C_{D\; C\; 2} > {\frac{{t_{0}t_{delay}} + {\frac{1}{2L}{V_{C\; 2}(0)}t_{delay}^{2}}}{{{Vs}\; 3^{*}} - {V_{c\; 1}(0)}} + \frac{\frac{1}{2L}\frac{\left( {{LI}_{0} + {{V_{C\; 2}(0)}t_{delay}}} \right)^{2}}{V_{clamp} - {V_{c\; 2}(0)}}}{{{Vs}\; 3^{*}} - {V_{c\; 1}(0)}}}},} & (5)\end{matrix}$

By using Equation (5), the capacitance of C_(DC2) can be determined andthat of C_(DC1) can be attained according to the relationship betweenC_(DC1) and C_(DC2) in different configurations. In symmetricconfiguration, C_(DC1)=C_(DC2); and in asymmetric configuration,C_(DC1)<C_(DC2).

MOV Selection.

Same as for the conventional SSCB, the diode clamped SSCB uses a MOV toabsorb energy during its breaking operation. Since the voltage acrossthe faulted transmission line is reduced by half in the diode clampedSSCB with symmetric configuration in comparison with conventional SSCBduring the operation of MOV, the clamp voltage of MOV along with theswitches block voltage can be lower than that needed in its counterpartof conventional SSCB. This advantage is even more dominant in a diodeclamped SSCB with the asymmetric configuration.

On the other hand, the energy absorbing capacity also should beconsidered during the selection of MOV. The energy absorbed in diodeclamped SSCB during the whole breaking time can be calculated by:

$\begin{matrix}{{W_{R} = {\int_{0}^{t_{mov}}{{V_{clamp}\left( {I_{0} + {\frac{V_{c\; 2}(0)}{L}t_{delay}} - {\frac{V_{clamp} - {V_{c\; 2}(0)}}{L}t}} \right)}{dt}}}},} & (6)\end{matrix}$

Where t=0 when switch S₄ opens and MOV starts to absorb energy. Aftert_(mov) in Equation (2) is introduced into Equation (6), the energyabsorbed W_(R) can be expressed as:

$\begin{matrix}{W_{R} = {\frac{1}{2}L\frac{V_{clamp}}{V_{clamp} - {V_{c\; 2}(0)}}{\left( {I_{0} + {\frac{V_{c\; 2}(0)}{L}t_{delay}}} \right)^{2}.}}} & (7)\end{matrix}$

From Equation (7), the value of W_(R) can be obtained by using severalparameters of the breaker and the transmission line. In comparison withthe needed energy capability of conventional breakers as depicted in:

$\begin{matrix}{W_{R} = {\frac{1}{2}L\frac{V_{clamp}}{V_{clamp} - V_{D\; C}}{I_{0}^{2}.}}} & (8)\end{matrix}$

the energy capability of the diode clamped SSCB can be lower in mostcases because the value of V_(C2)(0) is significantly smaller thanV_(DC) and the value of

$\frac{V_{c\; 2}(0)}{L}t_{delay}$

is usually negligible compared to I₀. In short, the MOVs that have arated voltage and clamping voltage higher than V_(C2) as well as energyabsorbing capability higher than W_(R) can be selected as the surgeprotectors for this topology.

Power Semiconductor Devices Selection.

To implement the diode clamped SSCB as shown in FIG. 3, several powersemiconductor devices including four active switching devices and twodiodes are needed. Their selection can be based on parameters includingvoltage rating, current rating and conducting efficiency. From thevoltage rating point of view, the switching devices S₂ and S₃ should beable to sustain the voltage value across capacitor C_(DC) 1; switchingdevices S₁ and S₄ should be capable of holding the clamping voltage ofthe MOV; and diodes D₁ and D₂ need to bear the voltage of C_(DC) 1during normal operation. In terms of current rating, all thesemiconductor devices should to be higher thanI₀+(V_(C2)(0)/L)t_(delay). In regard to conducting efficiency, IGBTs,GaN HEMTs, SiC MOSFETs and SiC JFETs with low R_(ds(on)) or V_(ds(on))are superior candidates as applied to solid-state circuit breakers atdifferent voltage levels.

Experimental Results

To validate the feasibility of the disclosed diode clamped SSCB, animage of an experimental setup of the breaker was fabricated as shown inFIG. 8. The components of the diode clamped SSCB according to FIG. 3 arelabeled in the image. In the setup of FIG. 8, the fabricated diodeclamped SSCB comprises Infineon's SiC MOSFETs (IMW120R045M), GeneSiC'sSiC Schottky Diodes (GC20MPS12), TDK's MOVs (B72240B0750K) and twocapacitors for voltage clamping.

In the experiment, the fabricated diode clamped SSCB was applied to atesting system with a 200V DC source and an 800 W pure resistive load.The transmission line between the source and load was modeled by a 1 mHinductor. The current interruption experiments of the breaker with bothsymmetric and asymmetric configurations were evaluated while operatingin the testing system and the experimental results are presented next.

Diode Clamped SSCB with Symmetric Configuration.

Two 1 mF capacitors were used to configure the diode clamped SSCB withsymmetric configuration. Examples of line current waveform and thevoltages across the line-side switches during the breaking process ofthe diode clamped SSCB are shown in FIG. 9. As seen in the plots of FIG.9, before t₁ the line current equals the rated load current and thevoltage across the two switches equals their forward conducting voltagesince both switches are turned on. During the interval from t₁ to t₂,line current decreases because switch S₃ is open causing the voltageacross the transmission line and load to decrease to V_(c2). After that,switch S₄ opens and the voltage across S₄ increases abruptly until it isclamped by the MOV. At last, the MOV absorbs the energy stored in thetransmission line inductor and line current decreases gradually until itreaches zero at t₃.

As seen from the experimental results, there is no dynamic overvoltageacross the switches during the interruption process even though the twoswitches are tripped sequentially with a time difference of 2.5×10-5second. Therefore, the experimental results validate that the diodeclamped SSCB does not have a dynamic voltage unbalancing issue in itscurrent breaking process.

Diode Clamped SSCB with Asymmetric Configuration.

Here, the diode clamped SSCB included two capacitors with values of 1 mFand 0.22 mF. FIG. 10 shows an example of the experimental results ofline current and switch voltages in the breaker with asymmetricconfiguration during its operation. From the waveform in FIG. 10, it canbe seen that the asymmetric configuration also does not incur dynamicvoltage unbalancing issue through its current interruption process.

Moreover, the current breaking time in the diode clamped SSCB is shorterwith asymmetric configuration. FIG. 11 shows a comparison of theexperimental results of line currents in diode clamped SSCBs withsymmetric and asymmetric configurations applied to the same testingsystem. As shown in FIG. 11, the line current breaks faster with theasymmetric configuration. This validates its advantage in breakingspeed.

The diode clamped SSCB topology is not limited to two levels; and inprincipal it can be extended to as many levels as needed, with alimiting factor being the availability of clamping diodes with theneeded reverse voltage blocking capability. This allows the diodeclamped SSCB architecture to work for even higher voltage levels usingthe same lower voltage devices. FIG. 12 is a schematic diagramillustrating an extension of the diode clamped SSCB topology to athree-level design, where the voltage rating of the SSCB is three timesthe rating of the semiconductor switches. Additional devices can beincorporated to further extend the topology as can be understood.

This disclosure has presented a new diode clamped SSCB topology. Unlikea conventional SSCB using series connected semiconductor devices formedium level voltage breaking, which incurs dynamic voltage unbalancingissues, the diode clamped SSCB utilizes a diode clamped structure toprotect the system while employing low voltage rated power semiconductordevices. The diode clamped SSCB topology does not experience dynamicvoltage unbalancing during its breaking operation. Symmetric andasymmetric configurations are presented. The asymmetric configurationcan shorten the current breaking time and reduce the energy absorptionof the diode clamped SSCB. The feasibility and superiority of the diodeclamped SSCBs with both symmetric and asymmetric configurations havebeen shown through simulations, algebraic analyses and experimentalresults. The attributes of the diode clamped SSCB make it a competitivealternative to conventional solid-state circuit breakers in mediumvoltage protection systems.

It should be emphasized that the above-described embodiments of thepresent disclosure are merely possible examples of implementations setforth for a clear understanding of the principles of the disclosure.Many variations and modifications may be made to the above-describedembodiment(s) without departing substantially from the spirit andprinciples of the disclosure. All such modifications and variations areintended to be included herein within the scope of this disclosure andprotected by the following claims.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the term “and/or” includes any and all combinations of oneor more of the associated listed items. As used herein, the singularforms “a,” “an,” and “the” are intended to include the plural forms aswell as the singular forms, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, steps, operations, elements, and/orcomponents, but do not preclude the presence or addition of one or moreother features, steps, operations, elements, components, and/or groupsthereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by onehaving ordinary skills in the art to which this invention belongs. Itwill be further understood that the terms, such as those defined incommonly used dictionaries, should be interpreted as having a meaningthat is consistent with their meaning in the context of the relevant artand the present disclosure and will not be interpreted in an idealizedor overly formal sense unless they are expressly so defined herein.

The term “substantially” is meant to permit deviations from thedescriptive term that do not negatively impact the intended purpose.Descriptive terms are implicitly understood to be modified by the wordsubstantially, even if the term is not explicitly modified by the wordsubstantially.

It should be noted that ratios, concentrations, amounts, and othernumerical data may be expressed herein in a range format. It is to beunderstood that such a range format is used for convenience and brevity,and thus, should be interpreted in a flexible manner to include not onlythe numerical values explicitly recited as the limits of the range, butalso to include all the individual numerical values or sub-rangesencompassed within that range as if each numerical value and sub-rangeis explicitly recited. To illustrate it, a concentration range of “about0.1% to about 5%” should be interpreted to include not only theexplicitly recited concentration of about 0.1 wt % to about 5 wt %, butalso include individual concentrations (e.g., 1%, 2%, 3%, and 4%) andthe sub-ranges (e.g., 0.5%, 1.1%, 2.2%, 3.3%, and 4.4%) within theindicated range. The term “about” can include traditional roundingaccording to significant figures of numerical values. In addition, thephrase “about ‘x’ to ‘y’” includes “about ‘x’ to about ‘y’”.

Therefore, at least the following is claimed:
 1. A diode clampedsolid-state circuit breaker (SSCB), comprising: a series of Nsource-side switches connected in series between a first DC sourceconnection and a common connection point, the series of N source-sideswitches comprising a first source-side switch connected to the first DCsource connection and a second source-side switch connected adjacent tothe first source-side switch; a series of N line-side switches connectedin series between a line-side connection and the common connectionpoint, the series of N line-side switches comprising a first line-sideswitch connected to the line-side connection and a second line-sideswitch connected adjacent to the first line-side switch; a series of Nclamping capacitors connected in series between a second DC sourceconnection and the common connection point, the series of N clampingcapacitors comprising a first clamping capacitor connected to the secondDC source connection and a second clamping capacitor connected adjacentto the first clamping capacitor; a source-side surge protector connectedacross the first source-side switch; a line-side surge protectorconnected across the first line-side switch; a source-side clampingdiode connected at a first end between the first and second source-sideswitches and at a second end between the first and second clampingcapacitors; and a line-side clamping diode connected at a first endbetween the first and second line-side switches and at a second endbetween the first and second clamping capacitors.
 2. The SSCB of claim1, comprising control circuitry configured to control switching of theseries of N source-side switches in response to a detected source-sidefault and the series of N line-side switches in response to a detectedline-side fault.
 3. The SSCB of claim 2, wherein the control circuitrycomprises gate drivers associated with the series of N source-sideswitches and the series of N line-side switches.
 4. The SSCB of claim 2,wherein the control circuitry sequentially turns off the series of Nsource-side switches from an N-th source-side switch to the firstsource-side switch in response to the detected source-side fault.
 5. TheSSCB of claim 4, wherein the control circuitry turns off the secondsource-side switch before turning off the first source-side switch. 6.The SSCB of claim 2, wherein the control circuitry sequentially turnsoff the series of N line-side switches from an N-th line-side switch tothe first line-side switch in response to the detected line-side fault.7. The SSCB of claim 6, wherein the control circuitry turns off thesecond line-side switch before turning off the first line-side switch.8. The SSCB of claim 2, wherein N is greater than two.
 9. The SSCB ofclaim 1, comprising a second source-side clamping diode connected at afirst end between the second source-side switch and a third source-sideswitch connected adjacent to the second source-side switch, and at asecond end between the second clamping capacitor and a third clampingcapacitor of the series of N clamping capacitors, the third clampingcapacitor connected adjacent to the second clamping capacitor; and asecond line-side clamping diode connected at a first end between thesecond line-side switch and a third line-side switch connected adjacentto the second line-side switch, and at a second end between the secondclamping capacitor and the third clamping capacitor.
 10. The SSCB ofclaim 9, comprising control circuitry configured to sequentially turnoff the series of N source-side switches in response to the detectedsource-side fault, wherein the control circuitry turns off the thirdsource-side switch before turning off the second source-side switch, andturns off the second source-side switch before turning off the firstsource-side switch.
 11. The SSCB of claim 9, comprising controlcircuitry configured to sequentially turn off the series of N line-sideswitches in response to the detected line-side fault, wherein thecontrol circuitry turns off the third line-side switch before turningoff the second line-side switch, and turns off the second line-sideswitch before turning off the first line-side switch.
 12. The SSCB ofclaim 1, wherein the first and second clamping capacitors have equalcapacitance.
 13. The SSCB of claim 1, wherein the first and secondclamping capacitors have different capacitances.
 14. The SSCB of claim13, wherein the capacitance of the first clamping capacitor is greaterthan the capacitance of the second clamping capacitor.
 15. A method,comprising: supplying DC voltage through a diode clamped solid-statecircuit breaker (SSCB) by turning on a series of N source-side switchesand a series of N line-side switches of the SSCB, the series of Nsource-side switches connected in series between a first DC sourceconnection and a common connection point and the series of N line-sideswitches connected in series between a line-side connection and thecommon connection point, the series of N source-side switches comprisinga first source-side switch connected to the first DC source connectionand a second source-side switch connected adjacent to the firstsource-side switch and the series of N line-side switches comprising afirst line-side switch connected to the line-side connection and asecond line-side switch connected adjacent to the first line-sideswitch, the SSCB further comprising a series of N clamping capacitorsconnected in series between a second DC source connection and the commonconnection point, N−1 source-side clamping diodes each connected betweendifferent pairs of adjacent source-side switches in the series of Nsource-side switches and different pairs of adjacent clamping capacitorsin the series of N clamping capacitors, and N−1 line-side clampingdiodes each connected between different pairs of adjacent line-sideswitches in the series of N line-side switches and the different pairsof adjacent clamping capacitors; detecting a source-side fault or aline-side fault; and sequentially turning off the series of Nsource-side switches from an N-th source-side switch to the firstsource-side switch in response to the detected source-side fault, wherethe second source-side switch is turned off before the first source-sideswitch is turned off to direct current flow through a first clampingcapacitor of the series of N clamping capacitors and one of the N−1source-side clamping diodes and the first source-side switch is turnedoff to the direct current flow through a surge protector connectedacross the first source-side switch; or sequentially turning off theseries of N line-side switches from an N-th line-side switch to thefirst line-side switch in response to the detected line-side fault,where the second line-side switch is turned off before the firstline-side switch is turned off to direct current flow through the firstclamping capacitor and one of the N−1 line side clamping diodes and thefirst line-side switch is turned off to the direct current flow througha surge protector connected across the first line-side switch.
 16. Themethod of claim 15, wherein N equals two and the series of N clampingcapacitors comprises the first clamping capacitor and a second clampingcapacitor, wherein the first and second clamping capacitors have equalcapacitance.
 17. The method of claim 15, wherein N equals two and theseries of N clamping capacitors comprises the first clamping capacitorand a second clamping capacitor, wherein a capacitance of the firstclamping capacitor is greater than a capacitance of the second clampingcapacitor.
 18. The method of claim 15, wherein sequentially turning offthe series of N source-side switches comprises turning off a thirdsource-side switch before the second source-side switch is turned off todirect current flow through the first clamping capacitor and a secondclamping capacitor and another one of the N−1 source-side clampingdiodes.
 19. The method of claim 15, wherein sequentially turning off theseries of N line-side switches comprises turning off a third line-sideswitch before the second line-side switch is turned off to directcurrent flow through the first clamping capacitor and a second clampingcapacitor and another one of the N−1 line-side clamping diodes.
 20. Themethod of claim 15, wherein each clamping capacitor of the series of Nclamping capacitors has a different capacitance.